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? february 2003 1/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 omnifet ii: fully autoprotected power mosfet 1 n linear current limitation n thermal shut down n short circuit protection n integrated clamp n low current drawn from input pin n diagnostic feedback through input pin n esd protection n direct access to the gate of the power mosfet (analog driving) n compatible with standard power mosfet description the vnn7nv04, vns7nv04, vnd7nv04 vnd7nv04-1, are monolithic devices designed in stmicroelectronics vipower m0-3 technology, intended for replacement of standard power mosfets from dc up to 50khz applications. built in thermal shutdown, linear current limitation and overvoltage clamp protects the chip in harsh environments. fault feedback can be detected by monitoring the voltage at the input pin. type r ds(on) i lim v clamp vnn7nv04 vns7nv04 vnd7nv04 vnd7nv04-1 60 m w 6 a 40 v sot-223 so-8 to251 (ipak) 1 2 2 3 1 3 3 2 1 to252 (dpak) block diagram overvoltage gate linear drain source clamp 1 2 3 current limiter control over temperature input fc01000 order codes package tube t&r sot-223 vnn7nv04 VNN7NV0413TR so-8 vns7nv04 vns7nv04 13tr to-252 (dpak) vnd7nv04 vnd7nv0413tr to-251 (ipak) vnd7nv04-1 -
2/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 absolute maximum rating connection diagram (top view) (*) for the pins configuration related to sot-223, dpak, ipak see outlines at page 1. current and voltage conventions symbol parameter value unit sot-223 so-8 dpak/ipak v ds drain-source voltage (v in =0v) internally clamped v v in input voltage internally clamped v i in input current +/-20 ma r in min minimum input series impedance 150 w i d drain current internally limited a i r reverse dc output current -10.5 a v esd1 electrostatic discharge (r=1.5k w , c=100pf) 4000 v v esd2 electrostatic discharge on output pin only (r=330 w , c=150pf) 16500 v p tot total dissipation at t c =25c 7 4.6 60 w e max maximum switching energy (l=0.7mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =9a) 40 40 mj e max maximum switching energy (l=0.6mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =9a) 37 mj t j operating junction temperature internally limited c t c case operating temperature internally limited c t stg storage temperature -55 to 150 c 1 so-8 package (*) drain drain drain drain input source source source 1 4 5 8 drain input source i d i in v in v ds r in
3/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 thermal data (*) when mounted on a standard single-sided fr4 board with 0.5cm 2 of cu (at least 35 m m thick) connected to all drain pins. on symbol parameter value unit sot-223 so-8 dpak ipak r thj-case thermal resistance junction-case }}} max 18 2.1 2.1 c/w r thj-lead thermal resistance junction-lead max 27 c/w r thj-amb thermal resistance junction-ambient max 96 (*) 90 (*) 65 (*) 102 c/w symbol parameter test conditions min typ max unit v clamp drain-source clamp voltage v in =0v; i d =3.5a 40 45 55 v v clth drain-source clamp threshold voltage v in =0v; i d =2ma 36 v v inth input threshold voltage v ds =v in ; i d =1ma 0.5 2.5 v i iss supply current from input pin v ds =0v; v in =5v 100 150 m a v incl input-source clamp voltage i in =1ma i in =-1ma 6 -1.0 6.8 8 -0.3 v i dss zero input voltage drain current (v in =0v) v ds =13v; v in =0v; t j =25c v ds =25v; v in =0v 30 75 m a symbol parameter test conditions min typ max unit r ds(on) static drain-source on resistance v in =5v; i d =3.5a; t j =25c v in =5v; i d =3.5a 60 120 m w electrical characteristics ( -40c < t j < 150c, unless otherwise specified) off 1
4/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 electrical characteristics (continued) (t j =25c, unless otherwise specified) dynamic switching source drain diode protections (-40c < t j < 150c, unless otherwise specified) (*) pulsed: pulse duration = 300 m s, duty cycle 1.5% symbol parameter test conditions min typ max unit g fs (*) forward transconductance v dd =13v; i d =3.5a 9 s c oss output capacitance v ds =13v; f=1mhz; v in =0v 220 pf symbol parameter test conditions min typ max unit t d(on) turn-on delay time v dd =15v; i d =3.5a v gen =5v; r gen =r in min =150 w (see figure 1) 100 300 ns t r rise time 470 1500 ns t d(off) turn-off delay time 500 1500 ns t f fall time 350 1000 ns t d(on) turn-on delay time v dd =15v; i d =3.5a v gen =5v; r gen =2.2k w (see figure 1) 0.75 2.3 m s t r rise time 4.6 14.0 m s t d(off) turn-off delay time 5.4 16.0 m s t f fall time 3.6 11.0 m s (di/dt) on turn-on current slope v dd =15v; i d =3.5a v gen =5v; r gen =r in min =150 w 6.5 a/ m s q i total input charge v dd =12v; i d =3.5a; v in =5v i gen =2.13ma (see figure 5) 18 nc symbol parameter test conditions min typ max unit v sd (*) forward on voltage i sd =3.5a; v in =0v 0.8 v t rr reverse recovery time i sd =3.5a; di/dt=20a/ m s v dd =30v; l=200 m h (see test circuit, figure 2) 220 ns q rr reverse recovery charge 0.28 m c i rrm reverse recovery current 2.5 a symbol parameter test conditions min typ max unit i lim drain current limit v in =5v; v ds =13v 6 9 12 a t dlim step response current limit v in =5v; v ds =13v 4.0 m s t jsh overtemperature shutdown 150 175 200 c t jrs overtemperature reset 135 c i gf fault sink current v in = 5v; v ds =13v; t j =t jsh 15 ma e as single pulse avalanche energy starting t j =25c; v dd =24v v in =5v; r gen =r in min =150 w; l=24mh (see figures 3 & 4) 200 mj 2
5/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 protection features during normal operation, the input pin is electrically connected to the gate of the internal power mosfet through a low impedance path. the device then behaves like a standard power mosfet and can be used as a switch from dc to 50khz. the only difference from the users standpoint is that a small dc current i iss (typ. 100 m a) flows into the input pin in order to supply the internal circuitry. the device integrates: - overvoltage clamp protection: internally set at 45v, along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. - linear current limiter circuit: limits the drain current i d to i lim whatever the input pin voltage. when the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . - overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cut-out occurs in the range 150 to 190 c, a typical value being 170 c. the device is automatically restarted when the chip temperature falls of about 15c below shut-down temperature. - status feedback: in the case of an overtemperature fault condition (t j > t jsh ), the device tries to sink a diagnostic current i gf through the input pin in order to indicate fault condition. if driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. if the drive impedance is high enough so that the input pin driver is not able to supply the current i gf , the input pin will fall to 0v. this will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current i iss . additional features of this device are esd protection according to the human body model and the ability to be driven from a ttl logic circuit. 1
6/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 figure 2: test circuit for diode recovery times l=100uh a b 8.5 w v dd r gen fast diode omnifet a d i s 150 w b omnifet d s i v gen figure 1: switching time test circuit for resistive load r gen v gen v d t i d 90% 10% t v gen t d(on) t d(off) t f t r
7/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 figure 3: unclamped inductive load test circuits figure 5: input charge test circuit figure 4: unclamped inductive waveforms r gen p w v in v in
8/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 1 source-drain diode forward characteristics derating curve static drain source on resistance static drain-source on resistance vs. input voltage transconductance 0 2 4 6 8 101214 id(a) 500 550 600 650 700 750 800 850 900 950 1000 vsd (mv) vin=0v 0 0.25 0.5 0.75 1 1.25 id(a) 0 50 100 150 200 250 300 350 400 450 500 rds(on) (mohm) tj=25oc tj=150oc tj= - 40oc vin=2.5v 33.544.555.566.5 7 vin(v) 0 10 20 30 40 50 60 70 80 90 100 110 120 rds(on) (mohm) id=3.5a tj=150oc tj= - 40oc tj=25oc 012345678 id(a) 0 2 4 6 8 10 12 14 16 18 20 gfs (s) vds=13v tj=25oc tj=150oc tj=-40oc 3 3.5 4 4.5 5 5.5 6 6.5 vin(v) 0 20 40 60 80 100 120 140 rds(on) (mohm) id=6a id=1a id=6a id=1a id=6a id=1a tj=25oc tj=150oc tj=-40oc static drain-source on resistance vs. input voltage
9/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 static drain-source on resistance vs. id turn on current slope transfer characteristics turn on current slope input voltage vs. input charge 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vin(v) 0 1 2 3 4 5 6 7 8 9 10 idon(a) vds=13.5v tj=150oc tj=25oc tj=-40oc 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 di/dt(a/us) vin=3.5v vdd=15v id=3.5a 00.511.522.533.544.555.56 id(a) 0 20 40 60 80 100 120 140 rds(on) (mohm) tj=25oc tj=150oc tj=-40oc vin=5v vin=3.5v vin=5v vin=5v vin=3.5v vin=3.5v 0 5 10 15 20 25 qg(nc) 0 1 2 3 4 5 6 7 8 vin(v) vds=12v id=3.5a 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 50 100 150 200 250 300 dv/dt(v/us) vin=5v vdd=15v id=3.5a turn off drain source voltage slope 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 1 2 3 4 5 6 7 8 di/dt(a/us) vin=5v vdd=15v id=3.5a
10/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 1 turn off drain-source voltage slope switching time resistive load output characteristics capacitance variations switching time resistive load normalized on resistance vs. temperature 100 200 300 400 500 600 700 800 900 1000 1100 rg(ohm) 0 50 100 150 200 250 300 dv/dt(v/us) vin=3.5v vdd=15v id=3.5a 0 5 10 15 20 25 30 35 vds(v) 100 200 300 400 500 600 c(pf) f=1mhz vin=0v 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 rg(ohm) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 t(us) td(on) tf td(off) tr vdd=15v id=3.5a vin=5v 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 vin(v) 0 200 400 600 800 1000 1200 1400 1600 t(ns) tf tr td(on) td(off) vdd=15v id=3.5a rg=150ohm 012345678910111213 vds(v) 0 1 2 3 4 5 6 7 8 9 10 11 12 id(a) vin=2.5v vin=4v vin=4.5v vin=3v vin=2v vin=5v -50 -25 0 25 50 75 100 125 150 175 t(oc) 0.5 0.75 1 1.25 1.5 1.75 2 2.25 rds(on) vin=5v id=3.5a
11/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 1 1 normalized input threshold voltage vs. temperature step response current limit current limit vs. junction temperature -50 -25 0 25 50 75 100 125 150 175 t(oc) 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 vin(th) vds=vin id=1ma 5 101520253035 vdd(v) 3.5 4 4.5 5 5.5 6 6.5 7 tdlim(us) vin=5v rg=150ohm -50 -25 0 25 50 75 100 125 150 175 tj (oc) 5 6 7 8 9 10 11 12 13 14 15 ilim (a) vds=13v vin=5v
12/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 so-8 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
13/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 dpak maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
14/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 sot-223 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 l(mh) i lmax (a) a b c
15/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 so-8 pc board r thj-amb vs pcb copper area in open box free air condition so-8 thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.14cm 2 , 0.6cm 2 , 1.6cm 2 ). so-8 at 4 pins connected to tab 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rthj_amb (oc/w)
16/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 sot-223 pc board r thj-amb vs pcb copper area in open box free air condition sot-223 thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.11cm 2 , 1cm 2 , 2cm 2 ). 60 70 80 90 100 110 120 130 140 00.5 11.5 22.5 cu area (cm^2) rth j-a mb (c/w)
17/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 dpak pc board r thj-amb vs pcb copper area in open box free air condition dpak thermal data layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: from minimum pad lay-out to 8cm 2 ). 30 40 50 60 70 80 90 0246810 pcb cu heatsink area (cm^2) rth j_amb (oc/w)
18/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 thermal fitting model of an omnifet ii in dpak pulse calculation formula thermal parameter area/island (cm 2 ) footprint 6 r1 (c/w) 0.1 r2 (c/w) 0.35 r3 ( c/w) 1.20 r4 (c/w) 2 r5 (c/w) 15 r6 (c/w) 61 24 c1 (w.s/c) 0.0006 c2 (w.s/c) 0.0021 c3 (w.s/c) 0.05 c4 (w.s/c) 0.3 c5 (w.s/c) 0.45 c6 (w.s/c) 0.8 5 z th d r th d z thtp 1 d C () + = where d t p t = dpak thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 6 cm 2
19/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 thermal fitting model of an omnifet ii in so-8 pulse calculation formula thermal parameter area/island (cm 2 ) footprint 2 r1 (c/w) 0.2 r2 (c/w) 0.9 r3 ( c/w) 3.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 3.00e-04 c2 (w.s/c) 9.00e-04 c3 (w.s/c) 7.50e-03 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 2 z th d r th d z thtp 1 d C () + = where d t p t = so-8 thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 2 cm 2
20/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 thermal fitting model of an omnifet ii in sot-223 pulse calculation formula thermal parameter area/island (cm 2 ) footprint 2 r1 (c/w) 0.2 r2 (c/w) 1.1 r3 ( c/w) 4.5 r4 (c/w) 24 r5 (c/w) 0.1 r6 (c/w) 100 45 c1 (w.s/c) 3.00e-04 c2 (w.s/c) 9.00e-04 c3 (w.s/c) 3.00e-02 c4 (w.s/c) 0.16 c5 (w.s/c) 1000 c6 (w.s/c) 0.5 2 z th d r th d z thtp 1 d C () + = where d t p t = sot-223 thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 t ime (s) zth (c/w) footprint 2 cm 2
21/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 1 1 dim. mm. inch min. typ max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a3 0.7 1.3 0.027 0.051 b 0.64 0.9 0.025 0.031 b2 5.2 5.4 0.204 0.212 b3 0.85 0.033 b5 0.3 0.012 b6 0.95 0.037 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 15.9 16.3 0.626 0.641 l 9 9.4 0.354 0.370 l1 0.8 1.2 0.031 0.047 l2 0.8 1 0.031 0.039 to-251 (ipak) mechanical data a c2 c a3 h a1 d l l2 l1 1 3 = = b3 b b6 b2 e g = = = = b5 2
22/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 dim. mm. inch min. typ max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 r 0.2 0.008 v2 0 8 0 8 to-252 (dpak) mechanical data = = = = = = = = e b2 l2 h l4 b g a c2 d r c a1 a2 v2 0.60 min. flat zone
23/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 dim. mm. inch min. typ max. min. typ. max. a 1.8 0.071 b 0.6 0.7 0.85 0.024 0.027 0.033 b1 2.9 3 3.15 0.114 0.118 0.124 c 0.24 0.26 0.35 0.009 0.01 0.014 d 6.3 6.5 6.7 0.248 0.256 0.264 e2.3 0.09 e1 4.6 0.181 e 3.3 3.5 3.7 0.13 0.138 0.146 h 6.7 7 7.3 0.264 0.276 0.287 v10 (max) a1 0.02 0.1 0.0008 0.004 sot-223 mechanical data 0046067
24/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m 0.6 0.023 f 8 (max.) so-8 mechanical data
25/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 sot-223 tape and reel shipment (suffix 13tr) reel dimensions base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
26/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 so-8 tube shipment (no suffix) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions c b a
27/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 dpak footprint tube shipment (no suffix) a c b all dimensions are in mm. base q.ty 75 bulk q.ty 3000 tube length ( 0.5) 532 a 6 b 21.3 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) reel dimensions base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.7 3.0 1.8 1.6 2.3 2.3 6.7
28/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 1 ipak tube shipment (no suffix) all dimensions are in mm. base q.ty 75 bulk q.ty 3000 tube length ( 0.5) 532 a 6 b 21.3 c ( 0.1) 0.6 a c b
29/29 vnn7nv04 / vns7nv04 / vnd7nv04 / vnd7nv04-1 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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